The present invention relates to the field of semiconductor technology. Specifically, embodiments of the invention relate to semiconductor device electrostatic discharge (ESD) protection structures and manufacturing methods.
In the field of semiconductor technology, the electrostatic discharge (ESD) phenomenon is a major threat to the integrated circuit. With the decreasing device dimensions in semiconductor process technology, ESD protection design becomes more challenging and difficult in nanoscale CMOS technologies.
In conventional technologies, SCR (silicon-controlled rectifier) devices are widely used as ESD protection devices. FIG. 1 is a cross-sectional view of a conventional SCR device with equivalent circuits also illustrated. As shown in FIG. 1, a conventional SCR device includes an N-well 101 in the P-type substrate 100. An N+ diffusion region 104 and a P+ diffusion region 105 are located in P-type substrate 100. A P+ diffusion region 102 and an N+ diffusion region 103 are also located within the N-well 101. P+ diffusion region 102 is coupled to the anode of the SCR device. P+ diffusion region 102 and N+ diffusion region 103 are coupled to a first pad PAD1. An N+ diffusion region 103 provides an ohmic contact to N-Well 101. N+ diffusion region 104 is the cathode of the SCR device. A P+ diffusion region 105 provides an ohmic contact to P-type substrate 100. N+ diffusion region 104 and P+ diffusion region 105 are coupled to a second pad PAD2. In this example, PAD1 is used as an IO pad, and PAD2 is used as a ground pad.
In the above SCR device, when a positive ESD appears briefly on the IO pad (PAD1) and the ground pad (PAD2), the SCR device forms a low impedance discharge channel to shunt the ESD current.
However, the inventors have observed that, in semiconductor devices at 28 nm manufacturing process node and below, the conventional SCR devices often provide trigger voltages that are too high to protect the internal circuitry. In addition, the conventional SCR devices often have holding voltages that are too low and can be susceptible to latch-up effects.
There is a need for an improved SCR device structure.